Notizie
ISSCC: Transceivers for radar and communication
In an invited paper, MediaTek described the technological challenges of developing automotive surround-view radar systems for 360° proximity sensing for vehicles, concentrating on a 79GHz FMCW (frequency-modulated continuous-wave) radar transceiver, plus DSP, that it has fitten into a 16 x 25mm.
Then Uhnder of Austin Texas described a 77/79GHz MIMO (multple-input antennas multiple-output antennas) radar SoC with 12 transmitters and 8×2 receivers, allowing 92 virtual receivers to be created. The resulting radar, in a 28nm CMOS IC, has 60mm range resolution, 1° angular resolution and 0.099km/h speed resolution from Doppler measurements.
Belgian research lab Imec, with Delft University of Technology and Eindhoven University of Technology, were there to talk about a UWB (ultra-wide-band) radar for occupancy and vital sign detection which can measure heart rate at 5m range and respiration at 15m, while consuming an astonishingly low 680μW. Apparently burst-chirp operation and time-domain pre-distortion is responsible for a 100x power reduction from earlier attempts – chirp slope is fast at 0.7GHz/40ms with a 0.5MHzrms.
Imec always features heavily at ISSCC – it is world-class in chip making technology, chip design and end-application development. In the RF transceiver session it also presented a second paper – this time on a 28nm CMOS transceiver front-end with integrated antennas for 145GHz FMCW radars. The transmitter has a peak effective isotropic radiated power of 11dBm with a 3dB bandwidth of 127 to 154GHz. The receiver has an effective isotropic noise figure of 6dB and a 3dB bandwidth of 138 to 151GHz.
Hiroshima University, the Japanese National Institute of Information and Communication Technology and Panasonic have been working together on a short-range 300GHz data transceiver in 40nm CMOS, which was revealed at the conference – which has achieved 80Gbit/s over 30mm using a pair of transceiver ICs with 24dBi horn antennas.
Intel was there with a 60GHz digital polar transmitter with on-chip pulse shaping. Built on 28nm CMOS, and using an on-PCB dual polariation antenna, it transmits spectrally-shaped 28.2Gbit/s data with 5.6dBm average power and -21.3dBm EVM while consuming 136mW.
And Intel was another organisation with two papers – the second of its describing a 71-76GHz 64-element phased-array with a direct-conversion 2×2 transceiver in 22nm finfet CMOS – said to be the first demonstration of a phased-array in finfet technology. It uses four ICs in a module that includes 16 patch antennas, with four of these modules tiled on a PCB to reach 64-elements. The final array has a measured EVM of -20dB for 7.2Gbit/s 16QAM at 35dBm effective isotropic radiated power.
Finally in the session, Korean research lab KAIST teamed up with Hanbat National University to present a 28GHz beam-forming front-end in 65nm CMOS. It has 6bit phase control with 1.5°rms phase error, and 16dB gain control range with 1.4° peak phase variation. The transmitter has a P1dB of 13.9dBm and a peak efficiency of 20.3%, and the receiver has a 4.58dB noise figure.
ISSCC
Held once a year in San Francisco, the IEEE International Solid-State Circuits Conference (ISSCC) is the the world’s showcase for innovative and cunning chip design. By inviting papers, and accepting others, the IEEE achieves a glorious spread of technology from companies and universities from all regions in the world where semiconductors are designed. is the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip.
Then Uhnder of Austin Texas described a 77/79GHz MIMO (multple-input antennas multiple-output antennas) radar SoC with 12 transmitters and 8×2 receivers, allowing 92 virtual receivers to be created. The resulting radar, in a 28nm CMOS IC, has 60mm range resolution, 1° angular resolution and 0.099km/h speed resolution from Doppler measurements.
Belgian research lab Imec, with Delft University of Technology and Eindhoven University of Technology, were there to talk about a UWB (ultra-wide-band) radar for occupancy and vital sign detection which can measure heart rate at 5m range and respiration at 15m, while consuming an astonishingly low 680μW. Apparently burst-chirp operation and time-domain pre-distortion is responsible for a 100x power reduction from earlier attempts – chirp slope is fast at 0.7GHz/40ms with a 0.5MHzrms.
Imec always features heavily at ISSCC – it is world-class in chip making technology, chip design and end-application development. In the RF transceiver session it also presented a second paper – this time on a 28nm CMOS transceiver front-end with integrated antennas for 145GHz FMCW radars. The transmitter has a peak effective isotropic radiated power of 11dBm with a 3dB bandwidth of 127 to 154GHz. The receiver has an effective isotropic noise figure of 6dB and a 3dB bandwidth of 138 to 151GHz.
Hiroshima University, the Japanese National Institute of Information and Communication Technology and Panasonic have been working together on a short-range 300GHz data transceiver in 40nm CMOS, which was revealed at the conference – which has achieved 80Gbit/s over 30mm using a pair of transceiver ICs with 24dBi horn antennas.
Intel was there with a 60GHz digital polar transmitter with on-chip pulse shaping. Built on 28nm CMOS, and using an on-PCB dual polariation antenna, it transmits spectrally-shaped 28.2Gbit/s data with 5.6dBm average power and -21.3dBm EVM while consuming 136mW.
And Intel was another organisation with two papers – the second of its describing a 71-76GHz 64-element phased-array with a direct-conversion 2×2 transceiver in 22nm finfet CMOS – said to be the first demonstration of a phased-array in finfet technology. It uses four ICs in a module that includes 16 patch antennas, with four of these modules tiled on a PCB to reach 64-elements. The final array has a measured EVM of -20dB for 7.2Gbit/s 16QAM at 35dBm effective isotropic radiated power.
Finally in the session, Korean research lab KAIST teamed up with Hanbat National University to present a 28GHz beam-forming front-end in 65nm CMOS. It has 6bit phase control with 1.5°rms phase error, and 16dB gain control range with 1.4° peak phase variation. The transmitter has a P1dB of 13.9dBm and a peak efficiency of 20.3%, and the receiver has a 4.58dB noise figure.
ISSCC
Held once a year in San Francisco, the IEEE International Solid-State Circuits Conference (ISSCC) is the the world’s showcase for innovative and cunning chip design. By inviting papers, and accepting others, the IEEE achieves a glorious spread of technology from companies and universities from all regions in the world where semiconductors are designed. is the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip.